was proposed in 1990 [7]. Contrary to the method of EMR detection this one
is based on introducing direct coupling of source and receiver. While CL is
in steady state it consumes current of about 10-9-10-8A which does not
allow OVD switching. The interface circuitry gets information on CL output
validity and in turn informs the environment about CL readiness to input
data processing. When an input data arrives CL changes its state to
"transient", current consumption increases to 10-4-10-2A, which switches
the OVD, thus informing the interface circuitry about output invalidity.
The latter lets the environment know about CL business.
After the computations in the CL are finished, the current consumption
decreases down to the steady state value, and the OVD sends a signal of
output validity.
4.1 Information carrying signal
Current consumption by CMOS CL contains useful information on CL
state. CMOS CL is a network of CMOS gates, so the current consumed by CL is
a superposition of currents consumed by CMOS gates included in the CL.
Each CMOS gate contains PMOS transistor and NMOS transistor networks
(Fig.5). While a gate is in a steady state either the PMOS or the NMOS
network is in a conducting mode. When a gate switches the non-conducting
transistor network becomes conducting. There is usually a short period in
switching time when both networks are in a conducting mode.
[pic]
Generally, current consumed by a CMOS gate includes three
components [9,10]:
(a) leakage current Ilk passing between power supply and ground due
to finite resistance of non-conducting transistor network;
(b) short-circuit current Isc flowing while both networks are in a
conducting mode;
(c) load capacitance CL charge current ILC flowing while a CMOS gate
is switching from low to high output voltage via conducting PMOS network
and CL .
SPICE simulation has shown [5] that amplitude of current consumed by
a typical CMOS inverter depends on CL and is limited by the non-zero
resistance of the conducting PMOS network (Fig.7). The integral of consumed
current is proportional to CL . When a gate switches from high to low
output voltage, the component ILC is negative by direction and negligible
by value (Fig.7b). It is evident, the switchings from high to low output
voltage occur at the expense of energy accumulated in CL during the
previous switching from low to high output voltage. The component Isc does
not depend on direction in which a gate switches.
The component ILC equals to ILC = CLVdd f where Vdd is a power
supply voltage, f is a gate switching frequency. Veendrick has investigated
the component Isc dependencies on CL and rise-fall time of input potential
signal [10]. He showed that if both input and output signal have the same
rise-fall time, the component Isc cannot be more than 20 percent of summary
current consumption [10]. However, when the output signal rise-fall time is
less than input one, the component Isc can be of the same order of
magnitude as ILC. In that case it must be taken into account. As to the
component Ilk, it entirely depends on CMOS process parameters and for state
of the art CMOS devices Ilk is about 10-15 -10-12 A.
So, the analysis of CMOS gate current consumption allows us to
conclude that in transient state a CMOS gate consumes a current I=
Ilk+Isc+ILC and in steady state it consumes only IlkVref, the
comparator output signal equals to logical "one" which means that the
outputs are invalid.
As it follows from the OVD circuit configuration,
[pic] [pic]
where Vdd is a voltage of power supply.
Equations (4) and (5) allow us to calculate the threshold voltage
drop V of the CVC circuit:
since [pic], so [pic] [pic]
If 0750mV, the diode D1 is in active mode and while rb 20, the component under
the sign of summation in Equation (7) can be much larger than the
component Cin. Due to voltage drop V the effective power supply voltage is
reduced and CL performance is decreased by about 35 percent [7].
In order to make SIM operating faster special attention must be paid
to reducing the capacitance introduced by CL.
4.3 Speed-independent address bus
The simplest case of CL is a scheme degenerated into a set of wires
called a multi-bit bus. Let us develop the OVD circuit for such a CL.
Multi-bit bus consists of several lines. Each line can be
considered as a medium for signal propagating from one end of the chip
to another. Delay of signal propagation through a line depends on several
factors:
(a) output impedance and symmetry of driver circuit;
(b) initial state of the line: if driver is symmetrical, line switching
from high to low voltage lasts shorter than reverse switching;
(c) electrical properties of the line as a signal propagation medium
(resistance of conducting layer and capacitances between the line and other
wires next to it);
(d) length of the line;
(e) input impedance and sensitivity of receiving circuit.
Since different lines of the bus operate in different conditions
(a)-(e), signal propagation delays are different, too. From the standpoint
of environment the bus behaves like any other more complicated CL.
Asynchronous RAM designers use a bus transition detector since 1980s
[13-15]. Such a detector is usually based on double-rail address coding
and two series connected transistors for each address bit [15]. One of
the transistors receives the true address signal and the other receives
the complementary address signal of the particular address bit. For any
steady state condition one of the transistors will be turned on and one
will be turned off. There will be a finite rise and fall time during a
transition of the address bit. There is a short time during which both
transistors are conducting. The establishment of the conductive path
provides the detection of the address transition. In the first
asynchronous RAMs the output signal of the transition detector is used for
bit line precharging and for enabling/disabling sense amplifiers and
peripheral circuitry.
Self-timed RAM announced in 1983 [14] used transition detectors not for
address transition only but also for detecting read/write completion and
address/bit line precharge completion as well.
The CMOS transition detector was invented in 1986 [15]. This circuit
is also based on double-rail coding and uses a pair of series-connected
NMOS transistors (Fig.12). The scheme for n-bit bus control contains n line
transition detectors (LTDs) and n AND-gates. Outputs of AND-gates are
united in node M forming wired OR. The output inverter serves as a pulse
shaper. Capacitors C1 and C2 are intended to prolong rise time of the LTD
output signal (true and complementary). This is necessary for reliable
detection.
The main drawback of the circuit is speed dependence. One can see
that if true and complementary address bit signal have different
propagation delays, the conducting path via NMOS transistors will never be
formed.
Using the OVD circuit proposed in Section 4.2 as LTD we can avoid
this drawback.
Note that address transmission through the address bus is
unidirectional. So to detect completion of bus transition it is enough to
recognize the bus state at the destination end. For this purpose we modify
CL to consist of n lines. The modification means introducing n LTDs, each
actually a CMOS inverter chain. Each chain contains two inverters loaded
with a capacitance (Fig.13). Input of each LTD is connected with
corresponding line of the bus at the destination end. Power supply pads of
all LTDs are connected to the current input of the same OVD circuit.
The parameters of the input current signal for the OVD circuit are
varied by
(i) value of capacitances C1 and C2 ;
(ii) dimensions of MOS transistors M1 -M4 .
Since all transitions in CL are of the same duration and can be
lengthened to be outlast the OVD turning-on time, we simplify the
interface circuitry by disallowing the asymmetrical delay.
Due to short duration of normal transition in this CL we must take
into account the integral nature of the sensitivity of the OVD circuit. OVD
sensitivity depends on both amplitude and width of input current pulse.
Simulated operation region of the OVD circuit for current pulses shorter
than 30ns is shown in Fig.14. It is obvious that in this case the threshold
of the OVD circuit must be determined by threshold charge Qth value. The
OVD input charge Q equals to [pic] where I is OVD input current, t is a
moment of time when transition occurs, w is a width of input current
pulse. Turning-on condition for the OVD circuit is Q=Qth.
When the LTD circuit shown in Fig.13 is used, the charge value Q is
determined by either C1 or C2. Namely, if the line goes from low to high
voltage, Q=VC2. If the line goes in the reverse direction then [pic] where
V is charging/discharging voltage, approximately equal to the effective
power supply voltage: VVdd -V. Here Vdd is OVD power supply voltage and V
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